Current efficient integrated architecture for common mode rejection sensitive neural recordings

In the last decade we have seen a significant growth of research and potential applications of electronic circuits that interact with the nervous system, in a wide range of applications, from basic neuroscience research to medical clinic, or from the entertainment industry to transport services. The real time acquisition and analysis of brain signals, either through wearable electroencephalography (EEG) or invasive or implantable recordings, in order to perform actions (brain machine interface) or to understand aspects of brain operation, has become scientifically and technologically feasible. This thesis aims to support neural recording applications with low noise, currentefficiency and high common-mode rejection ratio (CMRR) as main features of the recording system. One emblematic example of these applications in the neuroscience domain is the weakly electric fish neural activity recording, where the interference produced by the discharge of the fish electric organ is a key factor. Another example, from the implantable devices domain, is the nerve activity recorded with cuff electrodes, where the desired signal is interfered by electromyographic potentials generated by muscles near the cuff. In these cases, the amplitude of the interfering signals, which mainly appear in common mode, is several orders of magnitude higher than the amplitude of the signals of interest. Therefore, this thesis introduces a novel integrated neural preamplifier architecture targeting CMRR sensitive neural recording applications. The architecture is presented and analyzed in depth, deriving the preamplifier transfer function and the main design equations. We present a detailed analysis of a technique for blocking the input dc component and setting the high-pass frequency without using MOS pseudo-resistors. One of the main contributions of this work is the overall architecture coupled with an efficient and simple single-stage circuit for the preamplifier main transconductor. A fully-integrated neural preamplifier, which performs well in line with the state-ofthe-art of the field while providing enhanced CMRR performance, was fabricated in a 0.5 um CMOS process. Results from measurements show that the measured gain is 49.5 dB, bandwidth ranges from 13 Hz to 9.8 kHz, CMRR is very high (greater than 87 dB), and it is achieved jointly with a remarkable low noise (1.88 uVrms) and current-efficiency (NEF = noise efficiency factor = 2.1). A second version of the preamplifier with one external capacitor achieves a high-pass frequency of 0.1 Hz while keeping the performance of the fully-integrated version. In addition, we present in-vivo measurements made with the proposed architecture in a weakly electric fish (Gymnotus omarorum), showing the ability of the preamplifier to acquire neural signals from high amplitude common mode interference in an unshielded environment. This was the first in-vivo testing of a neural recording integrated circuit designed in Uruguay done in a local lab. Furthermore, signals recorded with our unshielded low-power battery-powered preamplifier perfectly match with those of a shielded commercially-available amplifier (ac-plugged, without power restrictions). To the best of our knowledge, the proposed preamplifier is the best option for applications that simultaneously need low noise, high CMRR and current-efficiency. Furthermore, in this thesis we applied the aforementioned architecture to bandpass biquad filters, specially but not only, to those with differential input. The new architecture provides a significant reduction in consumption (up to 30%) and/or makes it possible to block a higher level of dc at the input (up to the double, without using decoupling capacitors). Next, we applied the novel architecture to the design of the different stages of an integrated programmable analog front-end. Results from simulations shows that the gain is programmable between 57 dB and 99 dB, the low-pass frequency is programmable between 116 Hz and 5.2 kHz, the maximum power consumption is 11.2 uA and the maximum equivalent input-referred noise voltage is 1.87 uVrms. The comparison between our front-end and other works in the state-of-the-art shows that our front-end presents the best results in terms of CMRR and noise, has the greatest value of gain and equals the best NEF reported. Finally, some system-level topics were addressed during this thesis, including the design and implementation of three prototypes of end-to-end wireless biopotentials recording systems based on off-the-shelf components. Developing and applying circuits, systems and methods, for synchronized largescale monitoring of neural activity, sensory images, and behavior, would produce a dynamic picture of the brain function, which is essential for understanding the brain in action. In this context, we hope that the present thesis become our first step to further contribute to this area

Current-efficient preamplifier architecture for CMRR sensitive neural recording applications

Este trabajo fue parcialmente financiado por CSIC (Comisión Sectorial de Investigación Científica, Uruguay), ANII (Agencia Nacional de Investigación e Innovación, Uruguay) y CAP (Comisión Académica de Posgrado, Uruguay).There are neural recording applications in which the amplitude of common-mode interfering signals is several orders of magnitude higher than the amplitude of the signals of interest. This challenging situation for neural amplifiers occurs, among other applications, in neural recordings of weakly electric fish or nerve activity recordings made with cuff electrodes. This paper reports an integrated neural amplifier architecture targeting invivo recording of local field potentials and unitary signals from the brain stem of a weakly electric fish Gymnotus omarorum. The proposed architecture offers low noise, high common-mode rejection ratio (CMRR), current-efficiency, and a high-pass frequency fixed without MOS pseudoresistors. The main contributions of this work are the overall architecture coupled with an efficient and simple single-stage circuit for the amplifier main transconductor, and the ability of the amplifier to acquire biopotential signals from high-amplitude common-mode interference in an unshielded environment. A fully-integrated neural preamplifier, which performs well in line with the state-of-the-art of the field while providing enhanced CMRR performance, was fabricated in a 0.5 μm CMOS process. Results from measurements show that the gain is 49.5 dB, the bandwidth ranges from 13 Hz to 9.8 kHz, the equivalent input noise is 1.88 μVrms, the CMRR is 87 dB and the Noise Efficiency Factor is 2.1. In addition, in-vivo recordings of weakly electric fish neural activity performed by the proposed amplifier are introduced and favorably compared with those of a commercial laboratory instrumentation system

Enhanced ICMR amplifier for high CMRR biopotential recordings

PostprintThis paper presents an integrated biopotential preamplifier architecture targeting applications that simultaneously require high common-mode rejection ratio (CMRR), low noise, high input common-mode range (ICMR), and current-efficiency (low Noise Efficiency Factor or NEF). A biopotential preamplifier, which performs well in line with the state-of-the-art of the field while providing enhanced ICMR and CMRR performance, was fabricated in a 0.5 μm CMOS process. Results from measurements show that the gain is 47 dB, the bandwidth ranges from 1 Hz to 7.7 kHz, the equivalent input noise is 1.8 μV rms , the CMRR is 100.5 dB, the ICMR is 1.7 V and the NEF is 3.2

Relaxing the maximum dc input amplitude vs. consumption trade-off in differential-input band-pass biquad filters.

This paper shows that an important part of the power consumption of a biquad band‐pass filter is associated with the feedback loop that fixes the high‐pass frequency and blocks the direct current (dc) input signals. The dc input amplitude that can be blocked is related to the maximum output current that one of the transconductors can provide, hence impacting on the required consumption through this effect. Then, a technique that efficiently blocks the dc input signal and fixes the high‐pass frequency is introduced and analyzed in depth. Moreover, an architecture for ultra‐low‐power differential‐input biquads is fully presented. The proposed architecture enables lowering the power consumption or blocking higher levels of dc input without jeopardizing the power consumption. Results show that the proposed architecture, compared with a traditional one, presents a 30% reduction in power consumption and more than doubles the dc input that can be blocked

Plataforma de investigación para el confinamiento virtual de bovinos

Existen varios antecedentes de alambrados virtuales que utilizan diversas técnicas para mantener confinado al ganado bovino dentro de un perímetro configurado de forma remota. Estas técnicas comparten un patrón común que consiste en colocar un dispositivo electrónico en el animal capaz de aplicar estímulos cuando éste se acerca a los límites pre-establecidos. El uso de descargas eléctricas como método de estimulación es ampliamente utilizado. En este trabajo se propone una solución compatible con el bienestar animal, que evita las descargas eléctricas, basada solamente en estímulos sonoros y táctiles (mediante un motor vibrador). Para ello, se desarrolló un sistema que comprende un dispositivo electrónico que se coloca en el cuello del animal, y es capaz de determinar su posición, estimularlo y enviar información en forma inalámbrica; un servidor central que es capaz de recibir, procesar y almacenar esa información; y una interfaz gráfica, a través de la cual se puede visualizar la posición del animal y configurar distintos parámetros para evaluar diversas metodologías de confinamiento virtual. Las pruebas realizadas en animales, sugieren que los estímulos propuestos no son inocuos, por lo que se estima, podrían lograr su cometido luego de un periodo de aprendizaje de los animales. La investigación sobre la eficacia de las metodologías de confinamiento de la plataforma desarrollada  será realizada en una próxima etapa por un equipo interdisciplinari

Diseño de Circuitos Integrados para interfaz neural

En la ultima decada se registra a nivel mundial un crecimiento importante de las investigaciones y potenciales aplicaciones de circuitos electronicos que interact uen con el sistema nervioso tanto con nes de investigacion en neurociencias, como con nes medicos u otros. Los avances vertiginosos en: miniaturizacion de los aparatos de registro de EEG y de otras formas de registro de la actividad del sistema nervioso, potencia de procesamiento, metodos de analisis de patrones, y conocimiento de la organizacion cerebral de las funciones cognitivas han reavivado el interes en desarrollar este tipo de aparatos. Uno de los desafos tecnicos mas importantes que plantea el procesamiento de estas señales neurales es lograr observar un numero alto de canales, a lo que se suman las exigencias de alcanzar los bajos niveles de ruido necesarios para trabajar con señnales tan pequeñas, resolver la integracion de altas constantes de tiempo en areas razonables, tener bajo consumo para poder actuar con fuentes pequeñas de energa y no generar calentamiento local de los tejidos. Asimismo, es fundamental que la electronica que procesa estas señales tenga alto CMRR para poder eliminar las señales de interferencia en modo comun y sea capaz de bloquear niveles de continua en la entrada mucho mayores a los niveles de señal. La presente tesis consistio en el diseño de un front-end para la adquisicion de señales neurales en un circuito integrado. El front-end se dividio en tres etapas: un preamplicador de bajo ruido, un ltro programable y un ltro de salida con alto rango lineal. El preamplicador se implemento hasta el nivel fsico y se envi o a fabricar. El resto de las etapas se implementaron y caracterizaron a nivel de esquematico. Se utilizo el proceso C5 0,50m de ON Semiconductor. Se utilizo una arquitectura para preamplicadores neurales, de tipo Gm-C que logra su caracterstica pasabanda de una forma eciente en terminos de area y consumo, permitiendo a la vez obtener altos valores de CMRR y bajos niveles de ruido. En el marco de esta tesis se caracterizo la arquitectura y se extendio su uso a ltros, mostrando su generalidad y versatilidad. En particular, se desarrollo la expresion analtica de la transferencia, la expresion de la frecuencia corte inferior y la condicion para evitar no linealidades de la tecnica aplicada para lograr la caracterstica pasabanda. Estos resultados permiten diseñar circuitos basados en esta arquitectura facilmente a partir de especicaciones. Asimismo, se exploraron tecnicas para programar su ganancia y su frecuencia de corte de superior. Se propusieron e implementaron mejoras a la arquitectura del preamplicador neural que permitieron bajar su consumo, su ruido y extender su ancho de banda. Estos cambios lograron que el preamplicador quede a nivel de otros en el estado del arte, e incluso en alguna dimension sea mejor. En efecto, de mantenerse las caractersticas simuladas en el circuito fabricado, superara a todos los circuitos reportados a la fecha, desde el punto de vista del consumo y el ruido para barrer el rango 0,1Hz 10kHz. El preamplicador de caracterstica pasabanda utilizado en la etapa de entrada del front-end presenta las siguientes caractersticas simuladas: ganancia en banda pasante 49,6dB, CMRR = 83dB, frecuencia de corte superior 9,6kHz y frecuencia de corte inferior 0,1Hz (con capacitor externo) y 18Hz (con capacitor integrado). Presenta un consumo de 8, 1A y un ruido equivalente a la entrada de 1,96Vrms, lo que se corresponde con un NEF = 2,191. Para la segunda etapa del front-end se dise~no un ltro pasabanda, cuya ganancia es programable entre 1V=V y 110V=V y su frecuencia de corte superior es programable entre 100Hz y 5kHz. Como etapa de salida, se dise~no un ltro pasabanda de alto rango lineal, que es capaz de manejar a su salida 0,97Vpp con una THD = 3,1 %. El front-end congurado para tener maxima ganancia (99,3dB) y maxima frecuencia de corte superior (5,2kHz), presenta una frecuencia de corte inferior de 20Hz (con capacitores totalmente integrados) y un CMRR = 82dB. Asimismo, presenta un consumo de 11, 2A y un ruido equivalente a la entrada de 1,46Vrms, lo que se corresponde con un NEF = 2,61. De mantenerse las caractersticas simuladas en el circuito fabricado, el front-end superara a todos los circuitos reportados a la fecha desde el punto de vista de la ganancia, igualando los mejores compromisos ruido-consumo y manteniendo una buena performance en las otras caractersticas. Por otra parte, la ganancia del front-end es programable entre 57,3dB y 99,3dB, su frecuencia de corte superior es programable entre 0,1kHz y 5,2kHz. El maximo consumo del front-end es 11,2A y su maximo ruido equivalente es 1,87Vrms. En resumen se propuso una solucion que alcanza, y en algun aspecto supera, el estado del arte en el tema, realizando aportes novedosos. En particular, se logro obtener un front-end integrado programable, que permite trabajar con un conjunto muy amplio de se~nales biopotenciales, brindando al usuario mucha exibilidad, aumentando signicativamente los contextos donde podra aplicarse

Biopotential monitoring

Biopotentials measurements are essential for biological research and biomedical monitoring of excitable tissues. This chapter provides an overview of biopotential monitoring, from the biological basis to the circuit and system techniques. Signal acquisition, processing, and transmission are fundamental capabilities of biomedical research and medical devices development. In these topics, integrated, low-power consumption systems for portable, wearable, or implantable monitoring of neural signals are taken as study case, presenting both current research trends and established solutions. Starting from the biological sources of the biopotentials, the main observation levels are presented. The design of the integrated front-end amplifier, which must cope with the tougher trade-offs, is discussed, and the system level requirements and alternatives for data acquisition, processing, and wireless transmission are summarized